Switching Regulator Design

Switching Regulator Design
James Zou
10/27/2008
On board level design, we need to pay attention to two most important issues: power and clock. These two issues will decide the board stability and quality. In this paper, we only address the power issue, especially, the switching regulator design. On a regular server motherboard based on Intel chipsets with BMC function, there are about 26 power planes. Among these power planes, there are 10 power planes whose power was supplied by switching regulators. To meet the EUP standard and energy star requirement, more switching regulators are needed to improve the power efficiency.
The older linear regulator required minimum and maximum ESR of the output capacitor. The new linear regulator only required the maximum ESR of the output capacitor to maintain the loop stability. For example, the LT1117 from Linear Technology Inc only required the ESR of output capacitor should be less than 0.5 ohm and a minimum of 10μF of tantalum or 50μF of aluminum electrolytic capacitor. If we chose a linear regulator according to its current requirement and added a big enough output capacitor, we rarely got problem.  Switching regulator design is more complicated. We will start with finding the transferring function. Based on the transferring function,we can make the Bode plots and obtain the stability conditions. Then we will discuss how to choose the capacitors, inductors, and compensation circuit.

Figure 1. Feedback Model of Switching Regulator (Buck Regulator)

Using the current continuity in the energy transfer inductor, we can classify the switching regulator into two modes: Continuous-conduction-mode (CCM) and discontinuous-conduction-mode (DCM). The CCM mode means that the current in the energy transfer inductor never goes to zero between switching cycles. In DCM mode the current goes to zero during part of the switching cycle. From transfer function point, we can say CCM system is a second order system and DCM system is a first order system. On the s-plane, CCM system has a right-half-plane zero and  DCM. does not have a right-half-plane zero. It means DCM system is always stable.
 According to the topologies of circuit, we can name eight classes of  switching regulators: buck, boost, buck-boost, no-inverting buck-boost, bridge, Watkins-Johnson, current-fed bridge and inverse of Watkins-Johnson. The buck DC-DC switching regulator is dominated on modern motherboard design. In this paper, we will only discuss the buck DC-DC converter. A regular feedback model of switching regulator (buck) is shown in Figure 1.
 To expand the detail of buck DC-DC switching regulator, we use Intersil’s ISL6535 as an example, as shown in Figure 2, to deduct the transfer function and analyze the stability.

Figure 2. The block diagram of Intersil’s ISL6535

The detail of modulator in Figure 1 is shown in Figure 3. The input to the modulator is the output of the error amplifier. The output of the modulator is the PHASE node. The transfer function of the modulator is the input voltage to the regulator VIN, divided by the peak-to-peak voltage of the oscillator, ΔVOSC:


The peak to peak voltage of the oscillator can be obtained in data sheet of ISL6535.

Figure 3. The Modulator

The detail of Output filter in Figure 1 is shown in Figure 4. In theory, it should include the resistor of load. To simplify the calculation, we ignore the load resistance. The output filter circuit consists of the output inductor and output capacitors. The parasitic property of the inductor, DCR, and the parasitic property of the capacitors, ESR, play very important roles in the output filter. It will affect the system stability. We include these two parts in the transfer function:

 

Figure 4. The Output Filter

From the equation of the output filter transfer function, we can see there are double poles and one zero on the s-plane. The double poles can be normalized as:

The amplitude and phase plots for G(s) are shown in Figure 5.

 

Figure 5. The amplitude and phase plots for G(s)

If we combine the modulator and output filter together, we got the open loop system as shown in Figure 6. The transfer function of the open loop system can be described as:


Figure 6. The open loop system

In Figure 5, we can see when Q becomes bigger, the amplitude of the gain at the resonant frequency becomes bigger and the phase change at the resonant frequency becomes sharper. It means at high value Q, the open system is hard to be stabilized. The value of Q is determined by the ESR and DCR. If the DCR and ESR are very small, the Q will be very big. From system stabilization point, it is not good to choose too low ESR capacitors and  too low DCR inductors. However, we need to meet the voltage static and transient tolerance of the chipsets. The ESR must be very low. The DCR will affect the power efficiency. To improve the power efficiency, the DCR is the lower, the better. We  choose the ESR and DCR first to meet the ripple and transient tolerance, then we will choose the compensation circuit to stabilize the system. To simplify the analysis of the open loop system, we made the asymptotic Bode plot of the open loop system gain in Figure 7.


Figure 7. The amplitude Bode plot for the open loop system gain

As shown in Figure 1, all the switching regulator system is a feedback system with compensation network. There are three main reasons to add the feedback path: (1) improving the stability, (2) lowering Zout for stiffer V(out) vs. I(out), (3) widening the bandwidth. However, if the feedback system is not properly designed, when the feedback becomes positive, the system will oscillate.
   
In switching regulator design, there are three kinds of compensation as shown in Figure 8, Figure 9 and Figure 10.


Figure 8. Type I Compensation.

Figure 9. Type II Compensation.

Figure 10. Type III Compensation.

In this paper, we only discuss the type II compensation. The transfer function of type II compensation can be described as

Figure 11 shows the asymptotic Bode plot for the type II compensation gain and Figure 12 shows the Bode plot for the type II compensation phase.

Figure 11. Asymptotic Bode plot for type II compensation gain.

Figure 12 Bode plot for type II compensation phase.

From Figure 12, we can see the type II compensation will give a 90 degree boost to the phase. This boost is very important because it will cancel part of the effects of the double poles at the resonant frequency.
The closing loop system with type II compensation is shown in Figure 13.

 

Figure 13. The closing loop with type II compensation.

The transfer function of the closing loop with type II compensation is:
The Bode plot of this closing loop system is shown in Figure 14.

 

Figure 14. The Bode plot for the closing loop system of switching regulator.

A control system is stable if a gain crossing 0 db with close to a –20dB/decade slope and a phase margin greater than 45 ˚ . The crossover frequencies should be in the range of 10% to 30% of the switching frequency, fSW. To explain this stability criterion, we will discuss the stability theory of generic negative feedback amplifier system as shown in Figure 15.

 

Figure 15. A negative feedback amplifier system.

The transfer function of this negative feedback amplifier system can be written as:

 

where AFB is the gain of the amplifier with feedback (the closed-loop gain), β is the feedback factor and AOL is the gain without feedback (the open-loop gain). The gain AOL is a complex function of frequency, with both magnitude and phase. Examination of this relation shows the possibility of infinite gain (interpreted as instability) if the product βAOL =  -1. (That is, the magnitude of  βAOL is unity and its phase is -180°, the so-called Barkhausen stability criterion). Bode plots are used to determine just how close an amplifier comes to satisfying this condition.
Lets define f0dB is the frequency where the magnitude of the product | βAOL | = 1 (in dB, magnitude 1 is 0 dB). The frequency f0dB is determined by the condition:

 

The measurement of proximity to instability is the phase margin. The Bode magnitude plot locates the frequency where the magnitude of |βAOL| reaches unity, denoted here as frequency f0dB. Using this frequency, the Bode phase plot finds the phase of  βAOL. If the phase of  βAOL( f0dB) >  -180°, the instability condition cannot be met at any frequency (because its magnitude is going to be < 1 when f = f180), and the distance of the phase at f0dB in degrees above -180° is called the phase margin. Then the stability criteria can be expressed as: at 0 dB crossing, the f0dB is above –180°. However, this criterion is sufficient to predict stability only for amplifiers satisfying some restrictions on their pole and zero positions (minimum phase systems), as Nyquist criterion described. If we added 45 ˚ phase margin, this stability criterion is sufficient always. This is how the 45˚ Phase margin comes from.
The output capacitor and output inductors together form a low pass filter responsible for smoothing the pulsating voltage at the phase nodes. The output filter must provide the transient energy until the regulator can respond. Because it has a low-bandwidth compared to the switching frequency, the output filter necessarily limits the system transient response. The output capacitor must supply or sink load current while the current in the output inductors increases or decreases to meet the demand.
The table 2-2 and table 2-5 are directly copied from Intel processor specification. From Table 2-2 and Table 2-5, we know:
di/dt = 100A/200ns  = 500 A/μS
 ΔVmax  =  2*19mV + (0.15V-0.07V) = 118 mV
 ΔI = 100A
The filter capacitor must have sufficiently low ESL and ESR so that:
ΔV  < ΔVmax

 

 

Once the output capacitors are selected, the maximum allowable ripple voltage, Vpp(MAX), determines the lower limit on the inductance, as shown in the following Equation:

 

 
……………………………………………………………………..Equation 1.
Where, ESR is the Equivalent Serial Resistance of the output capacitor, Vin is the input voltage, Vout is the output voltage, fs is the switching frequency, Vp-p(MAX) is the maximum allowable ripple voltage.
The current in the switching regulator inductor is shown in Figure 16. The duty cycle can be obtained from Figure 17 as:

 

Figure 16. Switching Regulator Inductor Current.

 
Figure 17. PWM wave form is filtered by LC circuit.

D  = Ton/ Tp  = Vout/Vin         ……………..Equation 2        
During the PWM is on, the voltage on the two ends of the inductor is  ΔV =Vin –Vout. From the differential equation of the inductor, we have:
ΔV   =  L (ΔI/ΔT)                         …………… Equation 3
L  =    ΔV * ΔT/ΔI             ……. Equation 4
ΔT  = D/fs              ………….Equation 5
  so we have:
                        L = (Vin –Vout)Vout/fs VinΔI         ……….Equation 6
here ΔI the current ripple in the inductor. For a constant loading current, the ripple current should be compensated by the capacitors. To meet the ripple voltage requirement, we have:
ΔI = Vp-p(MAX) / ESR           …….Equation 7
Substituting equation 7 into equation 6, we have
L = ESR(Vin –Vout)Vout/fs VinVp-p(MAX)          ………Equation 8               
This is the low limit of the inductor.
The upper limit of inductance is given in the following in-equalities:
The peak-to-peak difference of the inductor current waveform is referred to as the inductor ripple current, and the inductor is typically selected large enough to keep this ripple current less than 20% to 30% of the rated DC current. In summary, we choose the inductor based on:
 Maximum input voltage
 Output voltage
 Switching frequency
 Maximum ripple current
 Duty cycle
 Maximum load current
MOSFET power dissipation depends on the gate-drive voltage (VD), the on-resistance (RDSON), the total gate charge (QGATE), and the gate threshold voltage (VTH).
Switching loss is the major contributor to the high-side MOSFET power dissipation due to the hard switching transition every time it turns on.
The low-side MOSFET power dissipation is mostly attributed to the conduction loss. Switching loss is negligible due to the zero-voltage switching at turn-on and body-diode clamp at turn-off.
The upper-MOSFET switching loss will setup the upper limit for the switching frequency. The lower limit is established by the requirement for the fast transient response and small output-voltage ripple. Choose the lowest switching frequency that allows the regulator to meet the transient response requirement.
The input capacitors are responsible for sourcing the input current flowing into the upper MOSFETS. Their RMS current capacity must be sufficient to handle the current drawn by the upper MOSFETs that is related to duty cycle and the number of active phases.

Advertisements

About superjameszou

Hardware Design Engineer
This entry was posted in Uncategorized. Bookmark the permalink.

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s